A Reconfigurable Parallel Signature Analyzer for Concurrent Error Correction in DRAM
نویسنده
چکیده
An efficient strategy to utilize a parallel signature analyzer (PSA) for concurrent soft-error correction in DRAM’S is described. For a two-level w-bit, n-word memory system, the proposed technique needs only one additional chip as opposed to log, w + 2 in the conventional Hamming code. Such an error-correction circuit (ECC) significantly improves the reliability of the memory system.
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